1. Field of the Invention
The present invention relates to a method of forming a contact hole and a capacitor for a semiconductor device, and more particularly, to a method of forming a small contact hole through an interlayer dielectric (ILD) layer having a small critical dimension and a large step coverage, and a method of forming a capacitor of a semiconductor device using the method.
2. Description of the Related Art
With the increase in the level of integration of semiconductor devices, the need for interconnection patterns having a finer linewidth has increased. In the photolithography process for forming such a fine contact pattern, first a photoresist pattern having a critical dimension (CD) of about 200 nm can be formed using deeply penetrating ultraviolet rays. Then, a photoresist (PR) flow process is performed in order to form a photoresist pattern having a finer linewidth than the previously formed photoresist pattern. The thickness of the photoresist pattern decreases as a result of the flow process and the width of the contact hole exposing the underlayer becomes narrower, so that a pattern of the desired fineness can be formed in subsequent processing. According to this method, a wire pattern or a contact pattern having a CD of around 130 nm can be obtained.
However, the PR flow process for achieving a fine linewidth causes the following problems. A considerable part of the photoresist pattern, the thickness of which has been decreased by the flowing process, is etched when the layer under the photoresist pattern (an ILD layer made of silicon oxide for example) is dry etched. As a result, the desired shape of the mask pattern is lost. If excessive etching is performed, a part or all of the photoresist pattern may be removed from the top of the substrate, which may result in enlarging the width of the opening at the top of the contact holes more than desired. The sidewalls of the contact holes become slanted with an increase in depth of the hole, so that the width at the bottom of the contact hole is narrower than the width of the opening at the top of the holes. If this phenomenon is serious, the contact may have no opening at the bottom.
If there is no technical restriction on the thickness of the photoresist layer, merely forming a thicker photoresist layer can be one of the solutions for the above described problems. However, since the resolution of the exposure apparatus depends on the exposure light source used for the photolithography process, the thickness of the photoresist cannot be arbitrarily selected. Also, if excessive photoresist is deposited, the photoresist layer cannot be completely removed by the subsequent ashing process and the byproduct from the ashing process may refill the contact holes, so that the underlayer is not exposed in the contact holes.
Other problems may also arise. A photoresist pattern having a small CD is required to produce a small contact hole, but the process margin may not be enough during the photolithography process for such a purpose. Also, byproducts produced during the development step (e.g., residues or bubbles of scununy byproduct) may be deposited on the contact holes, so that the contact holes are not opened.
Such problems are serious in third generation products such as, for example, the 256 megabyte DRAM, a semiconductor device having a 0.17 design rule which requires a fine contact having a CD of 120 nm and a depth of 10,000 .ANG.. Thus, the problems described above, e.g., that the upper part of the contact is much broader than the lower part of the contact and that the contact hole is not opened, must be solved in third generation products.
Hereinafter, a conventional method for forming a contact and the problems thereof will be described with reference to the appended drawings. FIG. 1 is a vertical sectional view of a semiconductor device illustrating the formation of a photoresist pattern. An ILD layer 15 and an anti-reflection layer 20 are stacked in sequence on a semiconductor substrate 10, and then photoresist is deposited to a predetermined thickness T1 on the top surface of the resulting structure. A predetermined photolithography process is performed on the deposited photoresist to form a photoresist pattern 25 that exposes part of the layer under the photoresist layer, the anti-reflection layer 20, by a predetermined width W1. The anti-reflection layer 20 is for preventing light irradiated onto the surface of the semiconductor substrate from reflecting during the photolithography process performed to obtain the photoresist pattern 25.
FIG. 2 is a vertical sectional view illustrating a conventional photoresist flow process in which the width of the opening in the photoresist pattern, through which the anti-reflection layer is exposed, is reduced from W1 to W2. When the photoresist flow process is performed, the original photoresist pattern 25 (see FIG. 1) is deformed to a photoresist pattern 25a having a reduced thickness T2 (smaller than the thickness T1 shown in FIG. 1) and a reduced exposure width W2 (narrower than the width W1 shown in FIG. 1).
FIG. 3 is a vertical sectional view showing a contact hole passing through the ILD layer 15, formed by a conventional method. Using the photoresist pattern 25a of FIG. 2 as a mask, etching is performed to form a contact hole passing through the anti-reflection layer 20 and the ILD layer 15. Then the material layers 25a and 20 deposited on the ILD layer 15 are removed, resulting in the structure of FIG. 3. It can be seen in FIG. 3 that the lower width W.sub.b of the contact hole is narrower than the upper width W.sub.t of the contact hole. This is due to the slanted sidewalls of the contact hole. If the sidewalls slant too much, the bottom of the contact hole which exposes the semiconductor substrate or a lower interconnection level (not shown) may have no opening at all.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.